RTL Design Engineer – Interconnect & Network Datapath

ABOUT THE TEAM OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. Building on efforts like Jalapeño, the team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. ABOUT THE ROLE We are looking for a highly experienced, hands-on RTL engineer with deep packet-networking and interconnect expertise to own critical on- and off-chip communication components for our custom AI accelerator platform. You will drive the microarchitecture and RTL implementation of scalable on-chip fabrics connecting high-bandwidth compute, memory, and I/O subsystems, as well as purpose-built off-chip interfaces and protocols that enable custom computing at scale. The ideal candidate has recently owned production RTL for networking or packet-switched datapaths such as Ethernet switches, NICs, SmartNICs, network accelerators, RDMA/RoCE systems, NoCs, or custom scale-up/scale-out fabrics. This is a senior engineering role with broad technical ownership and substantial direct RTL work. You will drive designs from requirements and performance analysis through microarchitecture, SystemVerilog implementation, verification closure, physical design convergence, silicon bring-up, and production readiness. You will also plan and oversee the work of junior engineers and help develop productive engineering relationships with external partners. IN THIS ROLE, YOU WILL: - Own the microarchitecture, RTL design, and delivery of major packet-based interconnect and networking components, including NoC fabrics, switches, routers, bridges, protocol adapters, arbiters, queues, schedulers, buffers, and traffic-management logic. - Design mechanisms for routing, arbitration, ordering, flow control, congestion management, quality of service, packet scheduling, buffering, and performance monitoring. - Develop on-chip and off-chip interfaces, protocol bridges, and custom networking protocols or protocol extensions for scale-up and scale-out systems. - Perform substantial direct microarchitecture, SystemVerilog coding, simulation, and debug work. - Collaborate with architecture and performance teams to analyze traffic patterns, identify bottlenecks, and optimize latency, bandwidth, fairness, and utilization under realistic workloads. - Work with verification teams to develop coverage plans, assertions, stress scenarios, and debug strategies for highly concurrent packet and fabric behavior. - Partner with physical design teams on floorplan-aware design, pipeline strategy, timing closure, power, area, and physical congestion. - Collaborate with firmware, software, validation, and post-silicon teams through bring-up and production readiness. - Drive third-party engagements involving networking, interface protocols, and silicon IP while maintaining design quality and execution accountability. - Provide technical leadership through architecture and design reviews, documentation, mentoring, and reusable RTL methodologies. YOU MIGHT THRIVE IN THIS ROLE IF YOU HAVE: - Extensive industry experience with recent, hands-on ownership of complex networking, packet-processing, or packet-switched interconnect RTL. - Demonstrated networking expertise in one or more of the following: Ethernet switching, NIC/SmartNIC/DPU datapaths, network accelerators, RDMA/RoCE, InfiniBand, traffic management, or custom scale-up/scale-out transports. - Deep expertise in Verilog/SystemVerilog and the development of clean, parameterized, production-quality RTL. - A strong record of owning major RTL blocks or SoC subsystems from requirements and microarchitecture through tape-out and silicon bring-up. - Experience designing queues, arbiters, schedulers, buffers,…